plat1098

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Today, Intel officially launched 11 new, highly integrated 10th Gen Intel Core processors designed for remarkably sleek 2 in 1s and laptops. The processors bring high-performance artificial intelligence (AI) to the PC at scale, feature new Intel Iris Plus graphics for stunning entertainment and enable the best connectivity with Intel Wi-Fi 6 (Gig+) and Thunderbolt 3. Systems are expected from PC manufacturers for the holiday season.

"These 10th Gen Intel Core processors shift the paradigm for what it means to deliver leadership in mobile PC platforms. With broad-scale AI for the first time on PCs, an all-new graphics architecture, best-in-class Wi-Fi 6 (Gig+) and Thunderbolt 3 - all integrated onto the SoC, thanks to Intel's 10nm process technology and architecture design - we're opening the door to an entirely new range of experiences and innovations for the laptop."
-Chris Walker, Intel corporate vice president and general manager of Mobility Client Platforms in the Client Computing Group

10th Gen Intel Core processors are foundational to Intel's journey in enabling uncompromising and workload-optimized PC platforms with performance leadership across all vectors of computing. In addition to performance and responsiveness gains, AI, graphics, connectivity and I/O are optimized on the SoC for a solution that delivers a feature-rich suite of capabilities for OEMs to create laptops for people to watch, game and create more.

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plat1098

Level 10
Verified

InstLatX64 has posted a CPU dump of Intel's next-generation 10 nm CPUs codenamed Tiger Lake. With the CPUID of 806C0, this Tiger Lake chip runs at 1000 MHz base and 3400 MHz boost clocks which is lower than the current Ice Lake models, but that is to be expected given that this might be just an engineering sample, meaning that production/consumer revision will have better frequency.

Perhaps one of the most interesting findings this dump shows is the new L3 cache configuration. Up until now Intel usually put 2 MB of L3 cache per each core, however with Tiger Lake, it seems like the plan is to boost the amount of available cache. Now we are going to get 50% more L3 cache resulting in 3 MB per core or 12 MB in total for this four-core chip. Improved cache capacity can result in additional latency because of additional distance data needs to travel to get in and out of cache, but Intel's engineers surely solved this problem. Additionally, full AVX512 support is present except avx512_bf which supports bfloat16 floating-point variation found in Cooper Lake Xeons.



Personal note: the comments following the article are worth a read, as always. :LOL: