- Sep 17, 2013
- 1,492
For more than a year, information on AMD’s next-generation CPU architecture, codenamed Zen, has tantalized the company’s fans — and those who simply want a more effective competitor against Intel. Now, the first concrete details have begun to appear. And if they’re accurate, the next-generation chip could pack a wallop.
Bear in mind, this is a single leaked slide of the highest-end part. Not only could details change dramatically between now and launch, but the slide itself might not be accurate. Let’s take a look:
According to Fudzilla, the new CPU will offer up to 16 Zen cores, with each core supporting up to two threads for a total of 32 threads. We’ve heard rumors that this new core uses Simultaneous Multithreading, as opposed to the Clustered Multi-Threading that AMD debuted in the Bulldozer family and has used the last four years.
Each CPU core is backed by 512K of L2 cache, with 32MB of L3 cache across the entire core. Interestingly, the L3 cache is shown as 8MB contiguous blocks rather than a unified design. This suggests that Zen inherits its L3 structure from Bulldozer, which used a similar approach — though hopefully the cache has been overhauled for improved performance. The integrated GPU also supposedly offers double-precision floating point at 1/2 single-precision speed.
Supposedly the core supports up to 16GB of attached HBM (High Bandwidth Memory) at 512GB/s, plus a quad DDR4 controller with built-in DDR4-3200 capability, PCIe 3.0, and SATA Express support.
Too good to be true?
The CPU layout shown above makes a lot of sense. We’re clearly looking at a modular part, and AMD has defined one Zen “module” as consisting of four CPU cores, eight threads, 2MB of L2, and an undoubtedly-optional L3 cache. But it’s the HBM interface, quad-channel DDR4, and 64 lanes of PCIe 3.0 that raise my eyebrows.
Here’s why: Right now, the highest-end servers you can buy from Intel pack just 32 PCI-Express lanes. Quad-channel DDR4 is certainly available, but again, Intel’s high-end servers support 4x DDR4-2133. Server memory standards typically lag behind desktops by a fair margin. It’s not clear when ECC DDR4-3200 will be ready for prime time. That’s before we get to the HBM figures.
Make no mistake, HBM is coming, and integrating it on the desktop and in servers would make a huge difference — but 16GB of HBM memory is a lot. Furthermore, building a 512GB/s memory interface into a server processor at the chip level is another eyebrow-arching achievement. For all the potential of HBM — and make no mistake, it’s got a lot of potential –that’s an extremely ambitious target for a CPU that’s supposed to debut in 12 to 18 months, even in the server space.
Nothing in this slide is impossible, and if AMD actually pulled it off while hitting its needed IPC and power consumption targets, it would have an absolutely mammoth core. But the figures on this slide are so ambitious, it looks as though someone took a chart of all the most optimistic predictions that’ve been made about the computing market in 2016, slapped them together on one deck, and called it good.
I’ll be genuinely surprised if AMD debuts a 16-core chip with a massive integrated graphics processor, and 16GB of HBM memory, and 64 lanes of PCI-Express, and a revamped CPU core, and a new quad-channel DDR4 memory controller, and a TDP that doesn’t crack 200W for a socketed processor.
Bear in mind, this is a single leaked slide of the highest-end part. Not only could details change dramatically between now and launch, but the slide itself might not be accurate. Let’s take a look:
According to Fudzilla, the new CPU will offer up to 16 Zen cores, with each core supporting up to two threads for a total of 32 threads. We’ve heard rumors that this new core uses Simultaneous Multithreading, as opposed to the Clustered Multi-Threading that AMD debuted in the Bulldozer family and has used the last four years.
Each CPU core is backed by 512K of L2 cache, with 32MB of L3 cache across the entire core. Interestingly, the L3 cache is shown as 8MB contiguous blocks rather than a unified design. This suggests that Zen inherits its L3 structure from Bulldozer, which used a similar approach — though hopefully the cache has been overhauled for improved performance. The integrated GPU also supposedly offers double-precision floating point at 1/2 single-precision speed.
Supposedly the core supports up to 16GB of attached HBM (High Bandwidth Memory) at 512GB/s, plus a quad DDR4 controller with built-in DDR4-3200 capability, PCIe 3.0, and SATA Express support.
Too good to be true?
The CPU layout shown above makes a lot of sense. We’re clearly looking at a modular part, and AMD has defined one Zen “module” as consisting of four CPU cores, eight threads, 2MB of L2, and an undoubtedly-optional L3 cache. But it’s the HBM interface, quad-channel DDR4, and 64 lanes of PCIe 3.0 that raise my eyebrows.
Here’s why: Right now, the highest-end servers you can buy from Intel pack just 32 PCI-Express lanes. Quad-channel DDR4 is certainly available, but again, Intel’s high-end servers support 4x DDR4-2133. Server memory standards typically lag behind desktops by a fair margin. It’s not clear when ECC DDR4-3200 will be ready for prime time. That’s before we get to the HBM figures.
Make no mistake, HBM is coming, and integrating it on the desktop and in servers would make a huge difference — but 16GB of HBM memory is a lot. Furthermore, building a 512GB/s memory interface into a server processor at the chip level is another eyebrow-arching achievement. For all the potential of HBM — and make no mistake, it’s got a lot of potential –that’s an extremely ambitious target for a CPU that’s supposed to debut in 12 to 18 months, even in the server space.
Nothing in this slide is impossible, and if AMD actually pulled it off while hitting its needed IPC and power consumption targets, it would have an absolutely mammoth core. But the figures on this slide are so ambitious, it looks as though someone took a chart of all the most optimistic predictions that’ve been made about the computing market in 2016, slapped them together on one deck, and called it good.
I’ll be genuinely surprised if AMD debuts a 16-core chip with a massive integrated graphics processor, and 16GB of HBM memory, and 64 lanes of PCI-Express, and a revamped CPU core, and a new quad-channel DDR4 memory controller, and a TDP that doesn’t crack 200W for a socketed processor.
