- Oct 23, 2012
- 12,527
MIT researchers have today unveiled a prototype 36-core computing chip that dwarfs the dual-core or quad-core units found in the majority of computers, tablets and smartphones today. The chip works by utilizing a system dubbed 'network-on-a-chip', which enables data to pass between cores more quickly and efficiently than with the typical bus layouts of today.
The team explains on the MIT News blog how on a typical multi-core processor all data flows through a single wire. Only one core can communicate at a time and eventually, as the number of cores grows, it is found that they end up spending more time waiting for access to the bus to transfer data than they do actually processing.
In the new 'network-on-a-chip' design, the cores are arranged in a tiled grid layout and connected directly to adjacent cores. This means that data can travel across the chip over many different, varying paths to avoid cores that are busy or congested. The processor as a whole can operate much more efficiently.
However, an issue with the network-on-a-chip concept is that data could arrive at cores through many different, untraceable paths. This is a problem as sometimes cores on a processor need to access data stored in another core's cache before it is returned to the main memory.
The issue has been overcome by equipping the chip with a shadow network that allows cores to declare they are looking for a data packet in the same way that bus-powered chips normally do. The 36 cores on the chip are all assigned a priority to simulate the chronological ordering of requests found on bus layouts. You can read more about the specifics of the technology on the MIT site.
Although we won't be seeing our computers powered by 36-core processors for some time, the team intends to modify a version of Linux to run on their chip and see what actual applications operate like on this CPU architecture design. Afterwards, the blueprints will be released to the world as open-source hardware descriptor code for anybody to pick up and use.
Source: MIT
The team explains on the MIT News blog how on a typical multi-core processor all data flows through a single wire. Only one core can communicate at a time and eventually, as the number of cores grows, it is found that they end up spending more time waiting for access to the bus to transfer data than they do actually processing.
In the new 'network-on-a-chip' design, the cores are arranged in a tiled grid layout and connected directly to adjacent cores. This means that data can travel across the chip over many different, varying paths to avoid cores that are busy or congested. The processor as a whole can operate much more efficiently.
However, an issue with the network-on-a-chip concept is that data could arrive at cores through many different, untraceable paths. This is a problem as sometimes cores on a processor need to access data stored in another core's cache before it is returned to the main memory.
The issue has been overcome by equipping the chip with a shadow network that allows cores to declare they are looking for a data packet in the same way that bus-powered chips normally do. The 36 cores on the chip are all assigned a priority to simulate the chronological ordering of requests found on bus layouts. You can read more about the specifics of the technology on the MIT site.
Although we won't be seeing our computers powered by 36-core processors for some time, the team intends to modify a version of Linux to run on their chip and see what actual applications operate like on this CPU architecture design. Afterwards, the blueprints will be released to the world as open-source hardware descriptor code for anybody to pick up and use.
Source: MIT
