A recent patent
published by Intel (via
Underfox) may be the keystone for its future graphics accelerator designs - and it utilizes the Multi-Chip Module (MCM) approach. Intel
describes a series of graphics processors working in tandem to deliver a single frame. Intel's design points towards a hierarchy in workloads: a primary graphics processor coordinates the entire workload. And the company frames the MCM as a whole approach as a required step to guide silicon designers away from manufacturability, scalability, and power delivery problems that arise from increasing die sizes in the eternal search for performance.
According to Intel's patent, several graphics draw calls (instructions) travel to "a plurality" of graphics processors. Then, the first graphics processor essentially runs an initial draw pass of the entire scene. At this point, the graphics processor is merely creating visibility (and obstruction) data; it's deciding what to render, which is a high-speed operation to do on modern graphics processors. Then, a number of the tiles generated during this first pass go to the other available graphics processors. According to that initial visibility pass, they would be responsible for accurately rendering the scene corresponding to their tiles, which indicates what primitive is in each tile or shows where there is nothing to render.
